makefile - How to make "%" wildcard match targets containing the equal sign? -

the makefile wildcard system doesn't seem match targets if contain equal sign. there way work around deficiency? flag or setting or rule escape equal sign? know can not use equal sign i'd prefer fix idiosyncrasy of make if possible.

here's example of mean

$ cat makefile all:     echo dummy target b_%:     echo $@  $ make b_c=1   echo dummy target $ make b_c1   echo b_c1        

the first make command not match b_% though should. wasn't able find documentation supposed matched % wildcard. pointers? make version is

$ make --version                                                gnu make 3.81          copyright (c) 2006  free software foundation, inc.                                                                                                              program built i386-apple-darwin10.0                          

the problem here not % syntax, fact any command-line argument equals sign in interpreted variable assignment.

you should find if add dependency all: b_c=1, make all generate file fine.

there restrictions on file names can use make -- can't contain spaces or newlines, , e.g. backslashes problematic, (though not impossible accommodate simple use cases).

if absolutely have have file named this, suggested workaround use different name internally, , symlink external name last step of make recipe.