verilog - how to force data in design instead of using testbench -

hi guys wondering if there way force bit in design instead of using testbench? verilog code single port ram below how force ram[address] 1000 instead of using testbench?

module ram(clk, rst, w, r, data, address, read, read_out); parameter length = 4; parameter depth = 8; input clk, rst, r, w; input [length-1:0] data, address; output [length-1:0] read; output reg[length-1:0] read_out; reg[length-1:0] ram [depth-1:0]; assign read = ram[address];  always@(posedge clk) begin if (!rst) begin     if(w)     ram[address] <= data;     else if (r)     read_out <= ram[address]; end else begin     if (w)     ram[address] <= data; end end endmodule 

there procedural continuous assignment type of statements have precedence on procedural statements. these assign statements inside always block.

referring example in systemverilog lrm 1800-2012 section 10.6,

the assign procedural continuous assignment statement shall override procedural assignments variable. deassign procedural statement shall end procedural continuous assignment variable.

the value of variable shall remain same until variable assigned new value through procedural assignment or procedural continuous assignment.

so, can have combinational always block override existing value:

module ram... //... //... always@* begin //... logic  assign ram[address] = whatever_data // assign ram[address] = 'h1000; //... deassign ram[address]; //... end  always@ (posedge clk, negedge reset) begin //... //... // no change here. end  endmodule 

a new continuous assignment process created when line reached in procedural block.

assign can applied types reg, integer etc not on nets (force must used nets).

moreover, procedural continuous assignments synthesizable.

however, can misused , hence must used sparingly. better alternative find out other driving logic.

for more information, refer this , this links. while, procedural continuous assignment can found out @ systemverilog lrm ieee 1800-2012 section 10.6.